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caution electro-static sensitive devices bipolar analog integrated circuits pc2709tb 5 v, super minimold silicon mmic medium output power amplifier document n o . p 12653e j3v 0ds 0 0 (3rd edition) d ate p ubli shed n ovember 2000 n c p ( k ) data sheet the m a rk shows m a j or revi sed poi nts. description the pc2709tb i sasilicon m onolithic integrated circuits designed a s 1st i f a m plifier for d b s tuners. this i c i s pack age d i n supe r m i nim old packag e which i s s m aller than conventio nal m i nim old. the pc2709tb has com patible pin connections and perform ance t o pc27 0 9 t o f c onvention a l m i n i m o l d version. so, i n the case o f reducing your system size, pc2709tb is suitable to replace from pc27 0 9 t . these i c i s m anufactured using nec?s 2 0 g h z f t nesat?iii silicon bipolar process. this process uses silicon nitride passivation film and gold electrodes. these m aterials c a n protect chip surface from external pollution and prevent corrosion/m igration. thus, this i c has excellent perform ance, uniform ity and reliability. features ? h igh-density surface m ounting : 6-pin super m i nim old package (2.0 1.25 0.9 m m ) ? wideband response : f u = 2.3 g h z typ. @ 3 db bandwidth ? m edium output power : p o (sat) = + 11.5 dbm @ f=1 g h z with external inductor ? supply voltage : v c c = 4.5 to 5.5 v ? power gain : g p = 23 d b typ. @f = 1 g h z ? port i m pedance : input/output 5 0 applications ? 1st if a m plifiers in dbs converters ? r f s tage buffer in dbs tuners, etc. ordering information (pb-free) m r o f g n i y l p p u s g n i k r a m e g a k c a p r e b m u n t r a p 6-pi n s uper min imo l d c1e e m b o s s e d t ape 8 m m w i d e . 1 , 2 , 3 p i n s f a c e t h e perf orat i on s i d e o f t he t ape. q t y 3 k p cs/r eel. remark t o order evaluation sam ples, please contact your local s ales office (part num ber for s a m ple order: pc2709tb-a). p c 2709tb - e 3 - a the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version.
data sheet p12653ej3v0ds00 2 + + + + pc2709tb pin connections product line-up of 5 v-bias silicon mmic medium output power amplifier (t a = +25c, v cc =v out = 5.0 v, z s =z l = 50 1 1 1 1 ) part no. f u (ghz) p o (sat) (dbm) g p (db) nf (db) i cc (ma) package marking + pc2708t 6-pin minimold + pc2708tb 2.9 +10.0 15 6.5 @f = 1 ghz 26 6-pin super minimold c1d + pc2709t 6-pin minimold + pc2709tb 2.3 +11.5 23 5 @f = 1 ghz 25 6-pin super minimold c1e + pc2710t 6-pin minimold + pc2710tb 1.0 +13.5 33 3.5 @f = 0.5 ghz 22 6-pin super minimold c1f + pc2776t 6-pin minimold + pc2776tb 2.7 +8.5 23 6.0 @f = 1 ghz 25 6-pin super minimold c2l remark typical performance. please refer to electrical characteristics in detail. caution the package size distinguishes between minimold and super minimold. 3 2 1 4 c1e (top view) 5 6 4 5 6 3 (bottom view) 2 1 pin no. pin name 1input 2gnd 3gnd 4output 5gnd 6v cc
data sheet p12653ej3v0ds00 3 + + + + pc2709tb system application example example of dbs converters bs antenna (dbs odu) r e x i m . p m a f r if amp. oscillator pc2709tb parabola antenna to idu + example of 900 mhz band, 1.5 ghz band digital cellular telephone pc2709tb + demod. pll f/f pa sw i q driver = 2 0 $ 90 $ q i rx tx pll
data sheet p12653ej3v0ds00 4 + + + + pc2709tb pin explanation pin no. pin name applied voltage (v) pin voltage (v) note function and applications internal equivalent circuit 1 input < 1.05 signal input pin. a internal matching circuit, configured with resistors, enables 50 1 connec- tion over a wide band. a multi-feedback circuit is de- signed to cancel the deviations of h fe and resistance. this pin must be coupled to sig- nal source with capacitor for dc cut. 4outputvoltage as same as v cc through external inductor < signal output pin. the inductor must be attached between v cc and output pins to supply current to the internal output transistors. 6v cc 4.5 to 5.5 < power supply pin, which biases the internal input transistor. this pin should be externally equipped with bypass capacitor to minimize its impedance. 2 3 5 gnd 0 < ground pin. this pin should be connected to system ground with minimum inductance. ground pattern on the board should be formed as wide as possible. all the ground pins must be con- nected together with wide ground pattern to decrease impedance defference. note pin voltage is measured at v cc = 5.0 v 6 4 1 in v cc out gnd gnd 2 3 5
data sheet p12653ej3v0ds00 5 + + + + pc2709tb absolute maximum ratings t i n u s g n i t a r s n o i t i d n o c l o b m y s r e t e m a r a p v e g a t l o v y l p p u s cc t a v 6 6 d n a 4 n i p , c 5 2 + = total circuit current i cc t a a m 0 6 c 5 2 + = p n o i t a p i s s i d r e w o p d mounted on double copper clad 50 = 50 = 1.6 mm epoxy glass pwb (t a =+85c) 270 mw operating ambient temperature t a < 40 to +85 c storage temperature t stg < 55 to +150 c p r e w o p t u p n i in t a m b d 0 1 + c 5 2 + = recommended operating range k r a m e r t i n u . x a m . p y t . n i m l o b m y s r e t e m a r a p v e g a t l o v y l p p u s cc 4.5 5.0 5.5 v the same voltage should be applied to pin 4 and 6. operating ambient temperature t a < 40 +25 +85 c electrical characteristics (t a = +25c, v cc =v out = 5.0 v, z s =z l = 50 1 1 1 1 ) parameter symbol test conditions min. typ. max. unit i t n e r r u c t i u c r i c cc a m 2 3 5 2 9 1 l a n g i s t u p n i o n g n i a g r e w o p p b d 5 . 6 2 0 . 3 2 0 . 1 2 z h g 1 = f saturated output power p o (sat) f = 1 ghz, p in 5 . 1 1 + 0 . 9 + m b d 0 = < dbm z h g 1 = f f n e r u g i f e s i o n < 5.0 6.5 db upper limit o perating frequency f u 3 db down below flat gain at f = 0.1 ghz 2.0 2.3 < ghz 1 3 6 2 z h g 1 = f l s i n o i t a l o s i < db input return loss rl in 0 1 7 z h g 1 = f < db output return loss rl out 0 1 7 z h g 1 = f < db gain flatness 6 g p f = 0.1 to 1.8 ghz <( 1.0 < db
data sheet p12653ej3v0ds00 6 + + + + pc2709tb test circuit v cc 1 000 pf f p 0 0 0 1 f p 0 0 0 1 c 1 c 2 l 4 6 1 2, 3, 5 50 1 50 1 out in c 3 components of test circuit for measuring electrical characteristics example of actural application components y c n e u q e r f g n i t a r e p o e u l a v e p y t e u l a v e p y t c 1 to c 2 bias tee 1 000 pf c 1 to c 3 chip capacitor 1 000 pf 100 mhz or higher c 3 r e h g i h r o z h m 0 1 h n 0 0 3 r o t c u d n i p i h c l f p 0 0 0 1 r o t i c a p a c r e h g i h r o z h m 0 0 1 h n 0 0 1 h n 0 0 0 1 e e t s a i b l 10 nh 1.0 ghz or higher inductor for the output pin the internal output transistor of this ic consumes 20 ma, to output medium power. to supply current for output transistor, connect an inductor between the v cc pin (pin 6) and output pin (pin 4). select large value inductance, as listed above. the inductor has both dc and ac effects. in terms of dc, the inductor biases the output transistor with minimum voltage drop to output enable high level. in terms of ac, the inductor make output-port impedance higher to get enough gain. in this case, large inductance and q is suitable. capacitors for the v cc , input, and output pins capacitors of 1 000 pf are recommendable as the bypass capacitor for the v cc pin and the coupling capacitors for the input and output pins. the bypass capacitor connected to the v cc pin is used to minimize ground impedance of v cc pin. so, stable bias can be supplied against v cc fluctuation. the coupling capacitors, connected to the input and output pins, are used to cut the dc and minimize rf serial impedance. their capacitance are therefore selected as lower impedance against a 50 1 load. the capacitors thus perform as high pass filters, suppressing low frequencies to dc. to obtain a flat gain from 100 mhz upwards, 1 000 pf capacitors are used in the test circuit. in the case of under 10 mhz operation, increase the value of coupling capacitor such as 10 000 pf. because the coupling capacitors are determined by equation, c = 1/(2 / rfc).
data sheet p12653ej3v0ds00 7 + + + + pc2709tb illustration of the test circuit assembled on evaluation board c t u o n i c v cc c1e 13 2 64 5 mounting direction notes 1. 2. 3. 4. 30 = 30 = 0.4 mm double sided copper clad polyimide board. back side: gnd pattern solder plated on pattern : through holes top view amp-2 c l for more information on the use of this ic, refer to the following application note: usage and application of silicon medium-power high-frequency amplifier mmic (p12152e) . component list value c 1 000 pf l 300 nh
data sheet p12653ej3v0ds00 8 + + + + pc2709tb typical characteristics (unless otherwise specified, t a =+25c) 40 0 supply voltage v cc (v) circuit current i cc (ma) 35 30 25 20 15 10 5 123456 40 C60 operating ambient temperature t a ( $ c) circuit current i cc (ma) circuit current vs. operating ambient temperature 35 30 25 20 15 10 5 0 C40 C20 0 +20 +40 +60 +80 +100 no input signal v cc = 5.0 v 30 0.1 frequency f (ghz) power gain g p (db) noise figure, power gain vs. frequency 25 20 15 10 0.3 1.0 3.0 8 7 6 5 4 30 0.1 frequency f (ghz) power gain g p (db) power gain vs. frequency 25 20 15 10 0.3 1.0 3.0 v cc = 5.0 v 0 0.1 frequency f (ghz) isolation isl (db) isolation vs. frequency C50 0.3 1.0 3.0 0 0.1 frequency f (ghz) input return loss rl in (db) output return loss rl out (db) input return loss, output return loss vs. frequency C50 0.3 1.0 3.0 v cc = 5.0 v C10 C20 C30 C40 v cc = 5.0 v C10 C20 C30 C40 v cc = 5.5 v 5.0 v 4.5 v v cc = 5.0 v 5.5 v 4.5 v noise figure nf (db) g p nf C40 $ c t a = +25 $ c +85 $ c rl in rl out circuit current vs. supply voltage no input signal
data sheet p12653ej3v0ds00 9 + + + + pc2709tb +10 +15 +5 0 C5 C10 C15 C20 C30 C35 C25 C20 C15 C10 C5 0 +5 +10 input power p in (dbm) output power p out (dbm) f = 1.0 ghz +10 +15 +5 0 C5 C10 C15 C20 C30 C35 C25 C20 C15 C10 C5 0 +5 +10 input power p in (dbm) output power p out (dbm) output power vs. input power v cc = 5.0 v f = 1.0 ghz +85 $ c +10 +15 +5 0 C5 C10 C15 C20 C30 C35 C25 C20 C15 C10 C5 0 +5 +10 input power p in (dbm) output power p out (dbm) output power vs. input power f = 2.0 ghz 5.5 v +10 +15 +5 0 C5 C10 C15 C20 C30 C35 C25 C20 C15 C10 C5 0 +5 +10 input power p in (dbm) output power p out ( dbm) output power vs. input power v cc = 5.0 v 20 0 . 3 1 . 0 frequency f (ghz) saturated output power p o(sat) (dbm) saturated output power vs. frequency 18 16 14 12 10 8 6 4 2 0 0.3 1.0 5.5 v p in = 0 dbm v cc = 5.0 v 4.5 v 60 0 1 + 0 1 C output power of each tone p o(each) (dbm) 3rd order intermodulation distortion im 3 (dbc) 3rd order intermodulation distortion vs. output power of each tone f 1 = 1.000 ghz f 2 = 1.002 ghz 4.5 v v cc = 5.0 v 5.5 v 50 40 30 20 10 C8 C6 C4 C2 0 +2 +4 +6 +8 5.5 v v cc = 5.0 v 4.5 v t a = C40 $ c +25 $ c f = 2.0 ghz f = 1.0 ghz f = 0.5 ghz v cc = 5.0 v 4.5 v output power vs. input power remark the graphs indicate nominal characteristics.
data sheet p12653ej3v0ds00 10 + + + + pc2709tb s-parameters (t a =+25 $ $ $ $ c, v cc = v out =5.0v) s 11 -frequency 0.1 g 3.0 g 1.0 g s 22 -frequency 0.1 g 3.0 g 1.0 g 2.0 g
data sheet p12653ej3v0ds00 11 + + + + pc2709tb typical s-parameter values (t a = +25c) v cc =v out = 5.0 v, i cc = 26 ma frequency s 11 s 21 s 12 s 22 k mhz mag.ang.mag.ang.mag.ang.mag.ang. 100.0000 0.227 0.2 13.698 C4.5 0.027 C1.0 0.196 0.9 1.37 200.0000 0.239 1.0 13.724 C9.6 0.027 3.1 0.207 2.2 1.36 300.0000 0.245 2.9 13.830 C14.5 0.026 4.7 0.212 4.1 1.38 400.0000 0.244 2.5 13.998 C19.9 0.027 7.8 0.223 3.4 1.32 500.0000 0.243 1.5 14.109 C25.0 0.026 9.8 0.234 2.1 1.33 600.0000 0.247 C1.5 14.246 C30.4 0.027 11.9 0.252 C0.4 1.26 700.0000 0.265 C3.2 14.538 C35.5 0.028 13.6 0.270 C2.3 1.20 800.0000 0.284 C3.6 14.703 C41.3 0.028 14.9 0.287 C4.6 1.15 900.0000 0.301 C3.3 15.051 C47.0 0.028 17.2 0.298 C7.4 1.10 1000.0000 0.305 C2.4 15.331 C53.5 0.029 18.8 0.309 C11.9 1.05 1100.0000 0.299 C3.2 15.605 C60.0 0.029 20.9 0.322 C17.1 1.04 1200.0000 0.300 C6.3 15.773 C66.7 0.029 22.5 0.336 C21.5 1.01 1300.0000 0.314 C10.3 16.152 C74.0 0.030 23.8 0.353 C24.8 0.95 1400.0000 0.328 C14.4 16.282 C81.0 0.030 26.1 0.353 C28.8 0.93 1500.0000 0.354 C17.3 16.337 C89.3 0.032 25.6 0.368 C35.5 0.86 1600.0000 0.359 C19.5 16.370 C96.5 0.031 26.8 0.370 C41.8 0.86 1700.0000 0.373 C22.1 16.256 C104.5 0.033 28.0 0.382 C46.9 0.81 1800.0000 0.371 C26.8 15.977 C112.7 0.032 29.3 0.381 C52.8 0.83 1900.0000 0.379 C31.1 15.529 C120.5 0.033 31.3 0.378 C57.8 0.83 2000.0000 0.386 C36.0 15.307 C128.1 0.034 31.0 0.373 C64.1 0.82 2100.0000 0.387 C39.5 14 .745 C135.9 0.033 32.2 0.366 C70.8 0.85 2200.0000 0.374 C43.8 14.212 C143.7 0.033 30.5 0.363 C78.1 0.90 2300.0000 0.360 C48.7 13.633 C151.3 0.033 33.9 0.353 C83.0 0.94 2400.0000 0.339 C55.4 12.846 C158.7 0.032 35.5 0.331 C90.0 1.06 2500.0000 0.338 C62.0 11.990 C165.5 0.033 38.0 0.318 C95.6 1.11 2600.0000 0.334 C66.0 11.265 C172.1 0.033 39.1 0.304 C102.5 1.20 2700.0000 0.330 C69.0 10.560 C177.8 0.033 40.8 0.295 C108.3 1.25 2800.0000 0.311 C69.9 9.942 176.2 0.033 43.5 0.282 C113.7 1.36 2900.0000 0.291 C72.5 9.432 171.3 0.035 44.9 0.267 C118.6 1.40 3000.0000 0.258 C76.5 8.818 166.5 0.035 47.4 0.246 C125.1 1.55 3100.0000 0.240 C80.6 8.353 161.9 0.035 53.4 0.225 C131.2 1.64
data sheet p12653ej3v0ds00 12 + + + + pc2709tb package dimensions 6-pin super minimold (unit: mm) 0.9 ( 0.1 0.7 0 to 0.1 0.15 +0.1 C0.05 2.0 ( 0.2 1.3 0.65 0.65 0.2 +0.1 C0.05 2.1 ( 0.1 1.25 ( 0.1 0.1 min.
data sheet p12653ej3v0ds00 13 + + + + pc2709tb notes on correct use (1) observe precautions for handling because of electro-static sensitive devices. (2) form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation). all the ground pins must be connected together with wide ground pattern to decrease impedance difference. (3) the bypass capacitor should be attached to the v cc pin. (4) the inductor (l) must be attached between v cc and output pins. the inductance value should be determined in accordance with desired frequency. (5) the dc cut capacitor must be attached to input and output pin. recommended soldering conditions this product should be soldered under the following recommended conditions. for soldering methods and condi- tions other than those recommended below, contact your nec sales representative. l o b m y s n o i t i d n o c d e d n e m m o c e r s n o i t i d n o c g n i r e d l o s d o h t e m g n i r e d l o s infrared reflow package peak temperature: 235c or below time: 30 seconds or less (at 210c) count: 3, exposure limit: none note ir35-00-3 vps package peak temperature: 215c or below time: 40 seconds or less (at 200c) count: 3, exposure limit: none note vp15-00-3 wave soldering soldering bath temperature: 260c or below time: 10 seconds or less count: 1, exposure limit: none note ws60-00-1 partial heating pin temperature: 300c time: 3 seconds or less (per side of device) exposure limit: none note C note after opening the dry pack, keep it in a place below 25c and 65% rh for the allowable storage period. caution do not use different soldering methods together (except for partial heating). for details of recommended soldering conditions for surface mounting, refer to information document semiconductor device mounting technology manual (c10535e).

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